Toshiba provides the CPU, interface and memory subsystems necessary for SoC development.
The use of these subsystems allows you to dedicate your design resources to the development of differentiating features that is primary objective to develop a custom SoC.

ARM^® Cortex^®-Based CPU Subsystems

		SS_CPU_M4	SS_CPU_R4	SS_CPU_A53
CPU	CPU	Cortex-M4F	Cortex-R4	Cortex-A53
	# of cores	1	1	1
	L1 cache/core	-	I32KB D32KB	I32KB D32KB
	TCM/core	-	I32KB D32KB (configurable)	-
	L2 cache	-	-	256KB
	Interrupt controller	NVIC	VIC	GIC
	Bus IF master	AHB 32b x3	AXI 64b x1	AXI 128b x1
	Bus IF slave (inc. intr ctrl.)	-	AHB 32b x1 AXI 64b x1	AXI 32b x1
SRAM on bus		Configurable up to 2MB
DMAC		ARM DMA330 8ch
Timer		x10
UART		x2
I2C		Master x2 (Standard/Fast/Fast+), Slave x1
SPI flash memory IF		Single/Dual/Quad CS x2
SPI device controller		Master x2 Slave x1
GPIO		x64
Extension bus IF		Outbound AXI 128b x2, APB 32b x1 Inbound AXI 128b x1

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